Energy-efficient program layout for multi-bank architectures
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Energy conservation is an important problem for battery-powered embedded or portable systems. New technology such as RDRAM enables memory to operate at different power levels. This allows memory to be partitioned such that only the necessary parts of memory are in active mode, while the others are in low power modes. The traditional program layout has code and heap at one end, and stack at the other end. However, it is possible to place the code in the high address range (next to the stack) without loss of functionality. This thesis explores the energy impact of those two layouts in a partitioned power aware memory system and presents a static program analysis technique to predict the more energy-efficient layout for a given program. We verify the effectiveness of our analysis by running MiBench programs on an enhanced Simplescalar-based power simulator. Our experimental results show that the new layout saves up to 43% of the memory subsystem energy when compared to the traditional layout, with an average improvement of 12%, on a cache-less CPU(such as the widely used ARM7TDMI) . Our static analysis correctly predicts 13 out of 15 benchmarks from the MiBench suite. We also evaluate our scheme on a processor with several cache configurations. The cached configurations benefit much less (averaging less than 1%), though some programs see as much as a 25% energy savings from the non-traditional layout.